This page lists all the Keysight Technologies (Agilent HP) 1650A's on Although some items match several categories, all of them are listed here, no matter what category or subcategory they have been placed in. You may sort the listings from 1590.0 to 405.0 or in reverse. You also have the option of showing only ads that have been posted in the last 24 hours.
How to Find the Highest Quality and the Best Price
For a Larger View:
More Videos

Only show ads with images

Show ads from (mm/dd/yyyy)
Date Picker
Show ads until (mm/dd/yyyy)
Date Picker
Status: See All
GEO Zones: See All
Get Pricing and Quotes -
Hewlett Packard 1650A LOGIC ANALYZER $1100
Keysight (Agilent/HP) The 1650A Logic Analyzer does it all! It supp $405
AGILENT/HP 1650A $1590

Keysight Technologies (Agilent HP) 1650A Main Features and Specifications

Status Discontinued
Alternative 16800 Series Portable Logic Analyzer
Keysight Technologies (Agilent HP)

The HP 1650A is an 80-channel state/timing (25 MHz/100 MHz) logic analyzer, selectable in 16 channel groupings. The analyzer is capable of 100 MHz timing and 25 MHz state analysis on all channels.

The user interface consists of a panel keyboard with an RPG knob and a nine-inch white phosphor, high resolution CRT for information display. A 3 1/2 inch Sony disc drive, for setup storage and retrieval, is integral to the analyzer. An RS-232-C port and external scope trigger are available on the rear panel. The RS-232-C port is used for printer hardcopy output or for analyzer control via a controller.

  • State mode
    • Clock repetition rate: Single phase is 25 MHz maximum. With time or state counting, minimum time between states is 60 ns. Both mixed and demultiplexed clocking use master-slave clock timing - master clock must follow slave clock by at least 10 ns and precede the next slave clock by >50 ns
    • Clock pulse width: ≥10 ns about the threshold
    • Setup time: Data must be present prior to clock transition, ≥10 ns
    • Hold time: Data must be present after rising clock transition, 0 ns
  • State analysis
    • Data acquisition: 1024 samples / channel
    • Clock: Five clocks are available and can be used by either one or two state analyzers at any time. Clock edges can be ORed together and operate in single phase, two phase demultiplexing, or two phase mixed mode. Clock edge is selectable as positive, negative, or both edges for each clock
    • Clock qualifier: The high or low level of four clocks can be ANDed with the clock specification. Setup time: 20 ns, hold time: 5 ns
    • Pattern recognizers: Each recognizer is the AND combination of bit (0, 1, or X) patterns in each label. Eight pattern recognizers are available when one state analyzer is on. Four are available to each analyzer when two state analyzers are on
    • Range recognizers: Recognizes data that is numerically between or on two specified patterns (ANDed combination of zeros and/or ones). One range term is available and is assigned to the first state analyzer turned on. The maximum size is 32 bits
    • Qualifier: A user-specified term that can be anystate, nostate, a single pattern recognizer, range recognizer, or logical combination of pattern and range recognizers
    • Sequence levels: There are 8 levels available to determine the sequence of events required for trigger. The trigger term can occur anywhere in the first 7 sequence levels
    • Branching: Each sequence level has a branching qualifier. When satisfied, the analyzer will restart the sequence, or branch to another sequence level
    • Occurrence counter: Sequence qualifier may be specified to occur up to 65535 times before advancing to the next level
    • Storage qualification: Each sequence level has a storage qualifier that specifies the states that are to be stored
    • Enable/disable: Defines a window of post-trigger storage. States stored in this window can be qualified
    • Prestore: Stores two qualified states that precede states that are stored
    • State tagging: Counts the number of qualified states between each stored state. Measurement can be shown relative to the previous state or relative to trigger. Maximum count is 4.4 x 1012
    • Time tagging: Measures the time between stored states, relative to either the previous state or the trigger. Maximum time between states is 48 hours. With tagging on, the acquisition memory is halved - minimum time between states is 60 ns
    • Pattern symbols: User can define a mnemonic for the specific bit pattern of a label. When data display is SYMBOL, mnemonic is displayed where the bit pattern occurs. Bit pattern can include 0s, 1s, and dont cares
    • Range symbols: User can define a mnemonic covering a range of values. Bit pattern for lower and upper limits must be defined as a pattern of 0s and 1s. When data display is SYMBOL, values within the specified range are displayed as mnemonic + offset from base of range
    • Number of pattern and range symbols: 100 per analyzer
  • Timing mode: Minimum detectable glitch: 5 ns wide at the threshold
  • Timing analysis
    • Transitional timing mode: Sample is stored in acquisition memory only when the data changes. A time tag stored with each sample allows reconstruction of waveform display. Time covered by a full memory acquisition varies with the number of pattern changes in the data. Sample period: 10 ns. Maximum time covered by data: 5000 seconds. Minimum time covered by data: 10.24 µs
    • Glitch capture mode: Data sample and glitch information stored evey sample period. Sample period: 20 ns to 50 ms. Memory depth: 512 samples/channel. Time covered by data: Sample period x 512
    • Waveform display: Sec/div: 10 ns to 100 s - 0.01% resolution. Delay: -2500 s to 2500 s: presence of data dependent on the number of transitions in data between trigger and trigger plus delay. Accumulate: Waveform display is not erased between successive acquisitions
    • Overlay mode: Multiple channels can be displayed on one waveform display line. Maximum number of displayed waveforms: 24
    • Time interval accuracy: Channel to channel skew: 4 ns typical. Time interval accuracy: ±(sample period + channel-to-channel skew + 0.01% of time interval reading)
    • Asynchronous pattern: Trigger on an asynchronous pattern less than or greater than specified duration. Pattern is the logical AND of the specified low, high, or dont care for each assigned channel. If pattern is valid but duration is invalid, there is a 20 ns reset time before looking for patterns again
    • Greater than duration: Minimum duration is 30 ns to 10 ms with 10 ns or 0.01% resolution, whichever is greater. Accuracy is +0 ns to -20 ns. Trigger occurs at pattern + duration
    • Less than duration: Maximum duration is 40 ns to 10 ms with 10 ns or 0.01% resolution, whichever is greater. Pattern must be valid for at least 20 ns. Accuracy is +20 ns to -0 ns. Trigger occurs at the end of the pattern
    • Glitch/edge triggering: Trigger on glitch or edge following valid duration of asynchronous pattern while the pattern is still present. Edge can be specified as rising, falling, or either. Less than duration forces glitch and edge triggering off