Tektronix TLA6404

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The TLA6400 Series of portable logic analyzers combines high performance and affordability making it ideal for a wide range of embedded system debug and validation applications. The TLA6400 Series is available in 34, 68, 102, and 136 channel configurations and comes with 25 GS/s high-speed timing resolution, up to 667 MHz state timing, up to 64 MB record length, and the Tektronix exclusive iCapture functionality - all at a price point representing a significant price-performance breakthrough.

Higher signal speeds as well as shorter setup and hold times in digital systems have increased the timing resolution needed to characterize and debug timing issues. With 25 GS/s MagniVu (40 ps) high-resolution timing, the TLA6400 offers 6 times the timing resolution of other logic analyzers giving even the most cost conscious engineers the additional performance needed to accurately determine timing relationships between signals of interest. The TLA6400 also can capture buses with clock rates up to 667 MHz and data rates up to 1333 Mb/s.

The TLA6400 Series further enhances engineering productivity with advanced features like:

• iCapture^TM multiplexing that eliminates double probing with simultaneous digital and analog acquisition through a single logic analyzer probe
• Glitch trigger and storage that allows users to trigger on and display observed signal integrity faults
• iView^TM that provides seamless integration between the TLA6400 and over 100 Tektronix oscilloscopes to provide a time-correlated view of both logic analyzer and oscilloscope data on the same display

The TLA6400 also delivers quick and intuitive operation that saves time in busy lab environments. Usability features include a familiar Microsoft Windows 7 interface, drag and drop triggering and drag and drop measurements. These usability innovations have been proven to save time, remove complexity, and reduce measurement uncertainty.

The TLA6400 is well suited for a broad range of debug and analysis applications including signal integrity analysis, FPGA debug and verification, memory system validation, and embedded software integration and debug. The signal analysis solution is completed with the addition of new P5900 Series logic analyzer probes that offer lower capacitive loading (1 pF) to accurately acquire signals with faster edges without distorting the signal.

• 40 ps Resolution MagniVu™ Acquisition to Accurately See Signal Relationships in Your System
• State Speed – Sample your fastest synchronous buses with clock rates up to 667 MHz and data rates up to 1333 Mb/s
• 15 inch Display, with Optional Touch Screen to See More of Your Data and Navigate Efficiently through Your Data
• 4 Models with 34/68/102/136 Channels and Up to 64 MB Record Length offer Flexible Solutions to Fit Any Budget
• Drag-and-Drop Triggering – Simply drag any one of eight different trigger types from a table onto the waveform and the TLA will automatically set up the trigger conditions
• Drag-and-Drop Measurements – Simply drag an icon from the measurement toolbar and drop it on your signal of interest and get a table of results

The TLA6404 is a 136-channel logic analyzer module, with 25 GHz timing, 333 MHz state, and 2 MB record length. Options for up to 64 Mb record length and up to 667 MHz state are available.

TLA6404 characteristics:

• Number of channels: 136 (includes 4 clock and 4 qualifier). Clock channels can also be used as qualifiers
• State acquisition
  • Maximum state clock rate: 333 MHz (standard), 667 MHz (optional)
  • Maximum data rate: 667 Mb/s (standard), 1333 Mb/s (optional)
  • State record length with time stamps: 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB
  • Minimum clock pulse width: 250 ps
• Timing acquisition
  • MagniVu™ timing: 40 ps, adjustments to 80 ps, 160 ps, 320 ps, and 640 ps
  • MagniVu timing record length: 128 kB
  • Deep timing record length (half/full channels with time stamps and with or without transitional storage): 4/2 Mb, 8/4 Mb, 16/8 Mb, 32/16 Mb, 64/32 Mb, 128/64 Mb per channel
  • Deep timing resolution (half/full channel): 312.5 ps/625 ps to 50 ms
  • Channel-to-channel skew: 160 ps, typical
  • Minimum recognizable pulse/glitch width (single channel): 250 ps
  • Minimum detectable setup/hold violation: 80 ps
• Analog acquisition
  • Bandwidth: 2 GHz, typical
  • Attenuation: 10X or 5X
• Trigger
  • Independent trigger states: 16
  • Maximum independent If/Then clauses per state: 16
  • Maximum number of events per If/Then clause: 8
  • Maximum number of trigger events: 26 (2 counter/timers plus any 24 other resources)
  • Maximum triggerable data rate: 1333 Mb/s
  • Trigger machine sequence rate: DC to 800 MHz (1.25 ns)
  • Counter/timer range: 48 bits each
  • Counter rate: DC to 800 MHz (1.25 ns)
  • Timer clock rate: 800 MHz (1.25 ns)
  • Trigger event types: Word, Group, Channel, Transition, Range, Anything, Counter Value, Timer Value, Signal, Glitch, Setup-and-Hold Violation, Snapshot
  • Trigger action types: Trigger Module, Trigger All Modules, Trigger Main, Trigger MagniVu, Store, Don't Store, Store Sample, Increment Counter, Decrement Counter, Reset Counter, Start Timer, Stop Timer, Reset Timer, Snapshot Current Sample, Goto State, Set/Clear Signal, Do Nothing
• Display: 15 inch (38.1 cm) diagonal, active-matrix color TFT LCD with backlight, 1024x768 resolution
• Ports
  • External display port type: One DVI-I (primary – digital and analog) connector and one  VGA connector
  • Network Port: Two 10/100/1000 LAN with RJ-45 connector
  • USB Port: Five USB 2.0 ports and two USB 3.0 ports. USB ports can be disabled in BIOS