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HOME Test and Measurement Analyzers Logic Miscellaneous Logic Analyzers Agilent HP 16500B-16550A-16520A

Agilent HP 16500B-16550A-16520A

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Description of Agilent HP 16500B-16550A-16520A

Categories: Analyzers Logic, Miscellaneous Logic Analyzers

Manufacturer: Keysight Technologies (Agilent HP)

Model: 16520A

Condition: Used

Seller: Test Equipment Connection Corp.

Keysight (formerly Agilent) 16500B-16550A-16520A Logic Analysis System MainframeSystems

Logic Analysis System MainframeSystems configured to exact requirement Up to 1000 channels of 100 MHz state OR Up to 640 channels of 100 MHz timing with 1Mb/channel depth All data is time correlated Built-in hard drive with software preloaded Touch screen, keyboard & mouse user interfaces
Refurbished

Product specifications of Agilent HP 16500B-16550A-16520A (From Used-Line T&M Specifications)

  • Launch Date Jan-2049
  • See also 16521A
  • Status Discontinued by Manufacturer

The HP 16520A/16521A pattern generator is a general purpose digital stimulus. The module consists of one master card, or one master card and one or more expansion cards. The 16520A mastercard offers the minimum configuration of 12 data and three strobe channels, a clock out channel, and three dedicated input qualifier channels. The 16521A expansion card offers expandability with 48 additional data out channels. Up to four expansion boards (192 channels) can be connected to a single master board.

  • Three strobe output channels (10 ns minimum resolution)
  • Three input qualifier channels, and one input clock
  • 50 Mbit/s programmable pattern generation
  • 4 kbit per channel memory depth
  • Number of data channels: 12
  • Expandable to 204 data out channels (1 16520A and 4 16521As)
  • TTL and ECL interface levels
  • Maximum input voltage: ±40 V
  • Input impedance: 100 kΩ, 8 pF
  • Internally available clock rates between 5 kHz and 50 MHz
  • Intermodule trigger capability
  • Internal clock period: Programmable from 20 ns to 200 µs
  • External clock (provided by user)
    • Input clock period: 1 Hz to 50 MHz (20 ns minimum period) ECL or TTL, internal frequency divide provided
    • Duty cycle: 10 ns minimum high time, 10 ns minimum low time
  • Strobes
    • Number of strobes: 3
    • Bits/channel: 4095
    • Maximum bit rate: 20 Mbit/s (50 ns period)
  • Rise/fall time (typical)
    • ECL: 2.3 ns (-0.98 V to -1.55 V)
    • TTL: 2.5 ns (0.6 V to 2.7 V)
  • Channel-to-channel skew
    • Same card: ≤5 ns
    • Card-to-card: 10 ns
  • Editing: Delete, Merge, Copy, Insert
  • Listing bases: Binary, octal, decimal, hexdecimal, symbol
  • Data instruction set
    • Break: Stops program execution, last data vector is held at output
    • Repeat: Repeats vector up to 256 times
    • Wait IMB: Wait for intermodule trigger
    • Wait External: Wait for user-defined 3-bit pattern on external input pod to become true. No data cycle latency when pattern is true between 30 ns and 0 ns before next clock edge
    • Signal IMB: Arms other measurement cards
    • Macro: Four different macros may be defined and inserted as needed. Six character labels may be defined for each macro. Macros contain Repeat, Wait External, Wait IMB, Break, and Signal IMB instructions

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