Agilent HP AGI-16510B

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  •  Equipment Location : USA
Keysight/Agilent 16510B Logic Analyzer Module

Condition: Refurbished

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  • Description

    Keysight/Agilent 16510B STATE/TIMING CARD 80CH

    This product was manufactured by Keysight or one of its predecessors many years ago. We provide this page to assist you in using or replacing your product.

    If this product's status is "Discontinued": This product is no longer sold by Keysight, but is still fully supported. You can receive free enhanced self-support via the Keysight website or by calling or emailing the Keysight Contact Center. Repair and calibration agreements and per-incident services are available from Keysight Service Centers. Use the “Contact an Expert” link at the top of this page to learn more about your calibration & repair services or replacement options.

    If this product's status is "Obsolete": You can receive free self-support via the Keysight website only. Use the “Contact an Expert” link at the top of this page to learn more about your calibration & repair services or replacement options.


    (From Used-Line T&M Specifications )
      Keysight Technologies (Agilent HP) 16510B Specs (68.2 KB)
    Status Discontinued
    Alternative 16900 Series Modular Logic Analysis System

    The HP 16510B State/Timing Module is an 80 channel, 35 MHz state, 100 MHz timing logic analyzer. It can be configured as two independent state analyzers, or as one state and one timing analyzer.

    • Simultaneous state/state, or simultaneous state/timing analysis
    • Time interval; number of states; pattern search; minimum, maximum, and average time interval statistics
    • Uses transitional timing to store data only when there is a transition
    • Five clock inputs, 4 clock qualifiers, storage qualification, time and number of state tagging, and prestore
    • Small lightweight probing
    • Probes minimum swing: 600 mVp-p
    • State mode
      • Clock Repetition Rate: Single phase is 35 MHz maximum. With time or state counting, minimum time between states is 60 ns
      • Clock Pulse Width: ≥10 ns at threshold
      • Setup Time: Data must be present prior to clock transition, ≥10 ns
      • Hold Time: Data must be present after rising clock transition on all pods; 0 ns. Data must be present after falling clock transition on pods 1,3 and 5; 0 ns. Data must be present after falling clock transition on pods 2 and 4; 1 ns
    • Timing mode minimum detectable glitch: 5 ns wide at the threshold
    • Probes characteristics
      • Input RC: 100 KW ±2% shunted by approximately 8 pF at the probe tip
      • TTL Threshold Preset: +1.6 volts
      • ECL Threshold Preset: -1.3 volts
      • Threshold Range: -9.9 to +9.9 volts in 0.1V increments
      • Threshold Setting: Threshold levels may be defined for pods 1, 2, and 3 on an individual basis and one threshold may be defined for pods 4 and 5
      • Minimum Input Overdrive: 250 mV or 30% of the input amplitude, whichever is greater
      • Maximum Voltage: ±40 volts peak
      • Dynamic Range: ±10 volts about the threshold
    • State analysis
      • Data acquisition: 1024 samples / channel
      • Clocks: Five clocks are available and can be used by either one or two state analyzers at any time
      • Clock Qualifier: The high or low level of up to four clocks can be ANDed with the clock specification. Setup time: 20 ns; hold time: 5 ns
      • Pattern Recognizers: Each recognizer is the AND combination of bit (0, 1, or X) patterns in each label. Eight pattern recognizers are available when one state analyzer is on. Four are available to each analyzer when two state analyzers are on
      • Range Recognizers: Recognizes data which is numerically between or on two specified patterns (ANDed combination of 0s and/or 1s)
      • Qualifier: A user-specified term that can be anystate, nostate, a single pattern recognizer, range recognizer, or logical combination of pattern and range recognizers
      • Sequence Levels: There are eight levels available to determine the sequence of events required for trigger. The trigger term can occur anywhere in the first seven sequence levels
      • Branching: Each sequence level has a branching qualifier. When satisfied, the analyzer will restart the sequence or branch to another sequence level
      • Occurrence Counter: Sequence qualifier may be specified to occur up to 65535 times before advancing to the next level
      • Storage Qualification: Each sequence level has a storage qualifier that specifies the states that are to be stored
      • Enable/Disable: Defines a window of post-trigger storage
      • Prestore: Stores two qualified states that precede states that are stored
    • Tagging
      • State tagging: Counts the number of qualified states between each stored state. Maximum count is 4.4 x 1012
      • Time tagging: Measures the time between stored states, relative to either the previous state or the trigger. Maximum time between states is 48 hours
    • Timing analysis
      • Transitional timing mode—Sample is stored in acquisition memory only when the data changes. Sample period: 10 ns, maximum time covered by data: 5000 seconds, minimum time covered by data: 10.24 µs
      • Glitch capture mode—Data sample and glitch information stored every sample period. Sample period: 20 ns to 50 ms, memory depth: 512 samples / channel, time covered by data: sample period x 512
      • Waveform display—Sec/div: 10 ns to 100 s; 0.01% resolution, delay: ‑2500 s to 2500 s, maximum number of displayed waveforms: 24
      • Trigger—Asynchronous pattern: Trigger on an asynchronous pattern less than or greater than specified duration, Greater than duration: minimum duration is 30 ns to 10 ms, Less than duration: maximum duration is 40 ns to 10 ms, Glitch/edge triggering: trigger on glitch or edge following valid duration of asynchronous pattern while the pattern is still present
    • User interface control devices: knob on front panel, touchscreen fields, optional mouse
    • HP-IB and RS-232C interfaces for hardcopy printouts and control by a host computer


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