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HOME Test and Measurement Generators Pattern Generators Agilent HP KT-16720A_ER0

Agilent HP KT-16720A_ER0

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  • $2625

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Description of Agilent HP KT-16720A_ER0

Categories: Generators, Pattern Generators

Manufacturer: Keysight Technologies (Agilent HP)

Model: 16720A

Condition: Used

Keysight Technologies (formerly Agilent) 16720A Pattern Generator Card 300M Vectors/S (Used)

Keysight Technologies (formerly Agilent) 16720A Pattern Generator Card 300M Vectors/S (Used)
Product code: KT-16720A_ER0

Product specifications of Agilent HP KT-16720A_ER0 (From Used-Line T&M Specifications)

  • Launch Date Jan-2049
  • Pattern Depth Memory depth in vectors: 16 M / 8 M (half / full channel)
  • Channels 48-channels per module, connect up to 5 modules for 240 channels
  • Status --

The Agilent 16720A digital pattern generator module for Agilent´s 16900 Series and 16700 Series logic analysis systems is ideal for the functional testing of your digital design. The pattern generator is used to simulate infrequently encountered test conditions in hardware design and software program testing. You can also use a pattern generator to stimulate your electronic designs with ideal or faulty digital patterns for performing functional verification, debugging and stress testing.

  • Maximum stimulus clock: 300 MHz / 180 MHz (half / full channel)
  • Memory depth in vectors: 16 M / 8 M (half / full channel)
  • Maximum vector width: 120 bits / 240 bits (half / full channel)
  • Standard logic level support: TTL, CMOS, ECL, PECL, LVPECL, LVDS 3.3 V, 2.5 V, 1.8V
  • SynaptiCAD tools convert .VCD files into .PGB files directly
  • Convenient pattern entry with multiple number bases and pattern fills
  • INIT block, user-defined macros, and loops simplify vector entry and facilitate repetitive runs
  • Wait for External Event enables stimulus only when an external event occurs
  • 48-channels per module, connect up to 5 modules for 240 channels
  • Pattern Generator clock and data pods are ordered separately Pattern Generator Pods
  • Order at least one clock pod for each module used as a master, and at least one data pod for every 8 output channels
  • Compatible with 16900 and 16700 Series modular logic analyzers

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